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Features
* PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors * A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge * Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
* 5V/3.3V Regulator and Current Limitation Function * Reset Derived From 5V/3.3V Regulator Output Voltage * Sleep Mode With Supply Current of Typically < 45 A, Wake-up by Signal on Pins EN2 * * * * * *
or on LIN Interface A Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) LIN 2.1 Compliant 3.3V/5V Regulator with Trimmed Band Gap QFN32 Package
H-bridge Motor Driver ATA6823
1. Description
The ATA6823 is designed for several body and powertrain applications. The IC is used to drive a continuous current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a PWM signal and a direction signal and allows the use of the IC in a motor-control application. The PWM control is performed by the low-side switch; the high-side switch is permanently on in the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and interface high level). The window watchdog has a programmable time, programmable by choosing a certain value of the external watchdog resistor RWD, internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.1 is integrated.
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Figure 1-1.
Block Diagram
M
CP VRES CPLO Charge Pump CPIH
RGATE H2
RGATE H1 S1 S2
RGATE L1
RGATE L2 PGND GND
HS Driver 2
HS Driver 1
LS Driver 1
LS Driver 2 VBAT OT UV DG3 DG2 DG1 CC CC timer
VG PBAT VBAT VINT
12V Regulator
Supervisor
OTP 12 bit
OV
Vint 5V Regulator Oscillator
Logic Control
WD timer EN2
CP
VBAT VBG VBATSW VCC 5V Regulator LIN Bandgap VCC WD EN1 VCC VMODE /RESET DIR PWM RX TX LIN
Battery
Microcontroller
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2. Pin Configuration
Figure 2-1. Pinning QFN32
EN2 VBATSW VBAT VCC PGND L1 L2 PBAT VMODE VINT RWD CC /RESET WD GND LIN 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6823 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 TX DIR PWM EN1 RX DG3 DG2 DG1 VG CPLO CPHI VRES H2 S2 H1 S1
Note:
YWW ATA6823 ZZZZZ AL
Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin Description
Symbol VMODE VINT RWD CC /RESET WD GND LIN TX DIR PWM EN1 RX DG3 DG2 DG1 S1 H1 S2 H2 VRES I/O I I/O I I/O O I I I/O I I I I O O O O I/O O I/O O I/O Function Selector for VCC and interface logic voltage level Blocking capacitor 220 nF/10V/X7R Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Ground for chip core LIN-bus terminal Transmit signal to LIN bus from microcontroller Defines the rotation direction for the motor PWM input controls motor speed Microcontroller output to keep the chip in Active mode Receive signal from LIN bus for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R
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Table 2-1.
Pin 22 23 24 25 26 27 28 29 30 31 32
Pin Description (Continued)
Symbol CPHI CPLO VG PBAT L2 L1 PGND VCC VBAT VBATSW EN2 I/O I O I/O I O O I O I O I Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 1 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller, blocking capacitor 2.2 F/10V/X7R Supply voltage for IC core (after reverse protection) 100 PMOS switch from VVBAT Enable input
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3. Functional Description
3.1
3.1.1
Power Supply Unit with Supervisor Functions
Power Supply The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2). A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor provides the necessary low-voltage supply needed for the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator.
Note: The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator. A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the voltage is too low. There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on external voltage regulators, etc. 3.1.2 Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz. 3.1.3 Temperature Supervisor There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors. In case of detected overtemperature (150C), the diagnostic pin DG3 will be switched to "H" to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165C), the VCC regulator and all drivers including the LIN transceiver will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is 10C and there is a built-in hysteresis of about 10C to avoid fast oscillations. After cooling down below the 155C threshold; the IC will go into Active mode. The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically 165C.
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3.2
Sleep Mode
To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep mode, the following blocks are active: * Band gap * Internal 5V regulator (VINT) with external blocking capacitor of 220 nF * Input structure for detecting the EN2 pins threshold * Wake-up block of the LIN receive part
3.3
Wake-up and Sleep Mode Strategy
The IC has two modes: Sleep and Active. The change between the modes is described below. The default state after power-on is Active mode. The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active). The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver are permanently active to ensure a proper startup of the system. The Go to Active and Go to Sleep procedures are implemented as follows: * Go to Active by activating pin EN2 The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and VVBAT; for this reason the input voltage level must be positive and not higher than VVBAT. Pulling the EN2 pin up to the VVBAT level will drive the IC into Active mode. EN2 is debounced with a time constant of 20 s, based on a 100 kHz clock. * Go to Active using the LIN interface The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode, the LIN receiver is partially active. The wake-up by LIN requires 2 steps: 1. If the voltage on pin LIN is below a value of V/DATwake (about VVBAT - 2V) the receive part of the LIN interface is active (not to be confused with Active mode of the whole IC). The active receive part is able to detect a valid LOW on the LIN pin. 2. If LIN = LOW during a filter time twakeLIN (typically 70 s) the IC will change to Active mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without disturbing the Active mode. * Stay in Active via EN1 The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller. The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must be positive and not higher than VCC. EN1 cannot be used to switch from Sleep to Active because the VCC regulator is off in the Sleep mode and VCC will be zero. * Go to Sleep A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t gotosleep (typically 20 s) switches the IC to Sleep mode.
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Figure 3-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the activated receive block of the LIN interface. After going to Active mode, the VCC regulator starts working. Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for longer than tdb) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before. Figure 3-1. Wake-up by pin LIN
Active Mode Sleep Mode Active Mode
EN1
VCC
LIN
Tgotosleep = 20 s
Twakelin = 70 s
Regulator Wake-up Time
3.4
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 F ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage. The output voltage accuracy is in general < 3%; in the 5V mode with VVBAT < 9V it is limited to < 5%. To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 100 mA to 350 mA. The delivered voltage will break down and a reset may occur. Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink. A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low.
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Figure 3-2.
Correlation between VCC Output Voltage and Reset Threshold
5.15V 4.9V VCC1 4.85V VtHRESH 4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulated output voltage and the upper reset threshold voltage is higher than 75 mV (VMODE = HIGH) and higher than 50 mV (VMODE = LOW).
3.5
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external resistor RWD. The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of TWD. In order to save current consumption, the watchdog is switched off during Sleep mode.
Figure 3-3.
Timing Diagram of the Watchdog Function
tres tresshort
/RESET td t1 t2 t1 t2 td
WD
3.5.1
Timing Sequence For example, with an external resistor RWD = 33 k 1% we get the following typical parameters of the watchdog. TOSC = 12.32 s, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms 10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%.
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After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD. Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the time frame of t2 = 9.61 ms. The trigger event will restart the watchdog sequence. Figure 3-4. TWD versus RWD
60
50 max
typ
TWD (ms)
40
30 min 20
10
0 10 20 30 40 50 60 70 80 90 100
RWD (k)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < 10%. This means that t1 and t2 can also vary by 10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 x t1 = 10.87 ms, t1max = 1.10 x t1 = 13.28 ms t2min = 0.90 x t2 = 8.65ms, t2max = 1.10 x t2 = 10.57 ms Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms Twdmin = t1max = 13.28 ms Twd = 16.42 ms 3.15 ms (19.1%) Figure 3-4 above shows the typical watchdog period TWD depending on the value of the external resistor ROSC. A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
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3.6
LIN Transceiver
A bi-directional bus interface is implemented for data transfer between the LIN bus and the local LIN protocol controller. The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver.
3.6.1
Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin LIN. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: * Thermal shutdown active or overtemperature LIN active * Sleep mode
Figure 3-5.
Definition of Bus Timing Parameters
tBit TX
(input to transmitting Node)
tBit
tBit
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node 1
Thresholds of receiving node 2
tBus_dom(min) RX
(output of receiving Node 1)
tBus_rec(max)
trx_pdf(1) RX
(output of receiving Node 2)
trx_pdr(1)
trx_pdr(2)
trx_pdf(2)
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The recessive BUS level is generated from the integrated 30 k pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP). No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 k resistor in series with a diode to VBAT. 3.6.2 TXD Dominant Time-out Function The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced low longer than tdom > 18.4 ms, the pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 s) before switching LIN to dominant again.
3.7
3.7.1
Control Inputs EN1, EN2, DIR, PWM
Pins EN1, EN2 Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2 can withstand a voltage up to 40V. Internal pull-down resistors are included.
3.7.2
Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included.
3.7.3
Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.
Table 3-1.
ON 0 1 1 DIR X 0 1
Status of the IC Depending on Control Inputs and Detected Failures
Driver Stage for External Power MOS H1 OFF ON /PWM L1 OFF OFF PWM H2 OFF /PWM ON L2 OFF PWM OFF Standby mode Motor PWM forward Motor PWM reverse X PWM PWM Comments PWM
Control Inputs
The internal signal ON is high when * At least one valid trigger has been accepted (SYNC = 1) * VVBAT is inside the specified range (UV = 0 and nOV = 1) * The charge pump has reached its minimum voltage (CPOK = 1) and * The device is not overheated (OT2 = 0) In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10 s. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination.
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Table 3-2.
CPOK 0 X X X X Note:
Status of the Diagnostic Outputs
Device Status OT1 X 1 X X OV X X 1 X UV X X X 1 SC X X X X Diagnostic Outputs DG1 - - - - DG2 1 - 1 1 - DG3 - 1 - - - Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments
X X X 1 1 X represents: don't care - no effect) OT1: Overtemperature warning OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit CPOK: Charge pump OK
In order to be able to distinguish between a wake-up from LIN or from EN2, the source of wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1).
3.8
VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V.
3.9
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the output voltage on the reservoir capacitor is VVBAT plus VG. The charge pump is clocked with a dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC level.
3.10
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at 150C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature 165C the VCC regulator will be switched off and a reset occurs.
3.11
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS. The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the forward and reverse direction (see Table 3-1 on page 11). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in both directions.
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3.11.1 Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (s) = 0.41 x RCC (k) x CCC (nF) (tolerance: 5% 0.15 s) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The resistor RCC must be greater than 5 k and should be as close as possible to 10 k, the CCC value has to be 5 nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level. Figure 3-6. Timing of the Drivers
PWM or DIR
50%
t
tLxHL tLxf tLxLH tLxr
80%
Lx
20%
tCC
t
tHxLH tHxr tHxHL tHxf
tCC
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
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3.12
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time > tSC (typically 10 s) the signal SC (short circuit) will be set and the drivers will be switched off immediately. The diagnostic pin DG1 will be set to "H". With the next transition on pin PWM, the bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on again. There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1 will be set to "H". It will be cleared as above.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Pin Name Min. Max. Unit Ground GND 0 0 V Power ground PGND -0.3 +0.3 V Reverse protected battery voltage VBAT -0.3 +40 V Reverse protected battery voltage PBAT -0.3 +40 V V Digital output /RESET -0.3 VVCC + 0.3 V Digital output DG1, DG2, DG3 -0.3 VVCC + 0.3 4.9V output, external blocking capacitor VINT -0.3 +5.5 V Cross conduction time capacitor/resistor CC -0.3 VVINT + 0.3 V combination Digital input coming from microcontroller WD -0.3 VVINT + 0.3 V + 0.3 V Watchdog timing resistor RWD -0.3 VVCC Digital input direction control DIR -0.3 VVCC + 0.3 V V Digital input PWM control + Test mode PWM -0.3 VVCC + 0.3 V Digital input for enable control EN1 -0.3 VVCC + 0.3 Digital input for enable control EN2 -0.3 VVBAT + 0.3 V 5V regulator output VCC -0.3 +5.5 V V Digital input VMODE -0.3 VVINT + 0.3 12V output, external blocking capacitor VG -0.3 +16 V V Digital output RX -0.3 VVCC + 0.3 V Digital input TX -0.3 VVCC + 0.3 VVBAT + 2 V LIN data pin LIN -27(1) Source external high-side NMOS S1, S2 -2 +40(3) V VVG + 0.3 V Gates external low-side NMOS L1, L2 VPGND - 0.3 (2) (2) VSx + 16 V Gates of external high-side NMOS H1, H2 VSx - 1 Charge pump CPLO -0.3 VPBAT + 0.3 V V Charge pump CPHI -0.3 VVRES + 0.3 (4) V Charge pump output VRES -0.3 +40 V Switched VBAT VBATSW -0.3 VVBAT + 0.3 -40 +150 C Storage temperature STORE Notes: 1. For VVBAT 13.5V 2. x = 1.2 3. t < 0.5s 4. Load dump of t < 0.5s tolerated
5. Thermal Resistance
Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB(1) Note: Symbol Rthjc Rthja Value <5 29 Unit K/W K/W
1. Thermal resistance junction ambient: 29 K/W (at airflow of 0 LFPM), valid for JEDEC Standard 4-layer Thermal test board with 5 x 5 thermal via matrix (100 m drill hole, filled vias).
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6. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Normal functionality Normal functionality, overtemperature warning Drivers for H1, H2, L1, L2, and LIN are switched OFF, VCC regulator is OFF Note: 1. Full functionality 2. H-bridge drivers are switched off (undervoltage detection) 3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly 4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct 5. H-bridge drivers are switched off 6. Full LIN functionality in conformance with LIN specification 2.1
(1) (2) (3) (4) (5) (6)
Symbol VVBAT1 VVBAT2 VVBAT3 VVBAT4 VVBAT5 VVBAT6 Tj Tj Tj
Min. VTHUV 6 3 0 > VTHOV 7 -40 150 165
Max. VTHOV VTHUV <6 <3 40 18 +150 165 180
Unit V V V V V V C C C
7. Noise and Surge Immunity, ESD and Latch-up
Parameters Conducted interferences Conducted disturbances ESD according to IBEE LIN EMC - Pins LIN, PBAT, VBAT - Pin EN2 (33 k serial resistor) Standard and Test Conditions ISO 7637-1 CISP25 Test specification 1.0 following IEC 61000-4-2 6 kV 5 kV ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ESD- STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ESD STM5.3.1 - 1999 Value Level 4(1) Level 5
ESD HBM with 1.5 k/100 pF
4 kV
ESD HBM with 1.5 k/100 pF Pins EN2, LIN, PBAT, VBAT against GND ESD CDM (field induced method) Note: 1. Test pulse 5: Vbat max = 40V
8 kV
1 kV
Static latch-up tested according to AEC-Q100-004 and JESD78. * 3 to 6 samples, 0 failures * Electrical post stress testing at room temperature In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when not able to drive the specified current.
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8. Electrical Characteristics
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. 1 1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 1.7 1.7.1 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 Parameters Test Conditions Pin 25, 30 25, 30 2 3 30 30 30 30 30 Measured during qualification only VVBAT = 13.5V 30 31 Symbol IVBAT1 IVBAT2 VINT VBG VTHOV_UP VTHOV_DOWN VTOVhys VTHUV_UP VTHUV_DOWN VTUVhys RON_VBATSW 4.8 1.225 21.2 19.8 1 6.8 6.5 0.2 4.94 1.235 Min. Typ. Max. 7 50 5.1 1.245 22.7 21.3 2.4 7.4 7.0 0.6 100 Unit mA A V V V V V V V V Type* A A A A A A A A A A A Power Supply and Supervisor Functions Current consumption VVBAT VVBAT = 13.5V(1) Current consumption VVBAT VVBAT =13.5V in Standby mode Internal power supply Band gap voltage Overvoltage threshold Up VVBAT Overvoltage threshold Down VVBAT Overvoltage threshold hysteresis VVBAT Undervoltage threshold Up VVBAT Undervoltage threshold Down VVBAT Undervoltage threshold hysteresis VVBAT On resistance of VVBAT switch 5V/3.3V Regulator Regulated output voltage Regulated output voltage Line regulation Load regulation Output current limitation Serial inductance to CVCC including PCB 9V < VVBAT < 40V Iload = 0 mA to 100 mA 6V < VVBAT 9V Iload = 0 mA to 100 mA Iload = 0 mA to 100 mA Iload = 0 mA to 100 mA VVBAT > 6V 29 29 29 29 29 29 VCC1 VCC2 DC line regulation DC load regulation IOS1 ESL 100 1 4.85 (3.2) 4.75 (3.2) <1 <10 5.15 (3.4) 5.25 (3.4) 50 50 350 20 V V mV mV mA nH A A A A A D
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
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8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. 2.7 2.8 2.9 3 3.1 Parameters Serial resistance to CVCC including PCB Blocking cap at VCC HIGH threshold VMODE Reset and Watchdog VCC threshold voltage level VMODE = "H" for /RESET (VMODE = "L") 29 VtHRESH VVCC1-VtHRESH VtHRESL HYSRESth tres tresshort td tdelayRESL RRWD TOSC VILWD VIHWD VhysWD t1 0.7 x VVCC 0.3 980 x TOSC 0.7 0.5 75 (50) 4.3 (2.86) 70 200 6800 200 6800 2 350 (220) 4.9 (3.25) V A
(2), (3)
Test Conditions
Pin 29 29 1 1
Symbol ESR CVCC VMODE H VMODE L
Min. 0 1.1 0.7
Typ.
Max. 0.5 3.3 4.0
Unit F V V
Type* D D A A
2.10 LOW threshold VMODE
Tracking of reset threshold VMODE = "H" 3.1a with regulated output (VMODE = "L") voltage 3.2 3.3 3.4 3.5 3.6 3.7 VCC threshold voltage level VMODE = "H" for /RESET (VMODE = "L") Hysteresis of /RESET level Length of pulse at /RESET pin Length of short pulse at /RESET pin Wait for the first WD trigger Time for VCC < VtHRESL before activating /RESET Resistor defining internal bias currents for watchdog oscillator Watchdog oscillator period RRWD = 33 k VMODE = "H" (VMODE = "L")(4)
(5)
29
mV
A
29 29 5 5 5 29
V mV T100 T100 T100 s
A A A A A C
(5) (5) (4)
3.8 3.9
3 3 6 6 6
(5)
10 11.09
91 13.55 0.3 x VVCC
k s V V V
D A A A A A
Watchdog input 3.11 low-voltage threshold 3.12 3.13 Watchdog input high-voltage threshold Hysteresis of watchdog input voltage threshold
3.14 Close window
6
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
18
ATA6823
4856I-AUTO-02/10
ATA6823
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. Parameters Test Conditions
(5)
Pin 6 5 5
Symbol t2 VOLRES RPURES
Min.
Typ. 780 x TOSC
Max.
Unit
Type* A
3.15 Open window 3.16 3.17 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Output low-voltage of /RESET Internal pull-up resistor at pin /RESET
At IOLRES = 1 mA
0.4 5 10 15
V k
A A
LIN Transceiver, 7V VVBAT 18V Low-level output current High-level output current Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Pull up resistor to VS Current limitation Normal mode; VLIN = 0V, VRX = 0.4V Normal mode; VLIN = VVBAT VRX = VCC - 0.4V RLOAD = 1000 to VBAT VVBAT = 7.0V Rload = 500 VVBAT = 18V Rload = 500 VVBAT = 7.0V Rload = 1000 VVBAT = 18V Rload = 1000 serial diode required VBUS = VVBAT_max Input leakage current driver off VBUS = 0V VVBAT = 12V Driver off 7V < VVBAT < 18V 7V < VBUS < 18V VBUS = VVBAT 13 13 8 8 8 8 8 8 8 ILRXD IHRXD VBUSrecdrv V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM IBUS_PAS_dom 0.6 0.8 20 50 47 200 2 1 0.9 x VVBAT 1.2 2 mA mA V V V V V k mA A A A A A A A A A
Input leakage current at the receiver including 4.10 pull-up resistor as specified Leakage current LIN 4.11 recessive
8
-1
mA
A
8
IBUS_PAS_rec
20
A
A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
19
4856I-AUTO-02/10
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Leakage current at ground loss Control unit disconnected 4.12 from ground Loss of local ground must not affect communication in the residual network Node has to sustain the current that can flow under 4.13 this condition. Bus must remain operational under this condition 4.14 Center of receiver threshold
7V < VVBAT < 18V GNDDevice = VS VVBAT = 12V 0V < VBUS < 18V
8
IBUS_NO_gnd
-1
+1
mA
A
7V < VVBAT < 18V VVBAT disconnected VSUP_Device = GND 0V < VBUS < 18V 7V < VVBAT < 18V VBUS_CNT = (Vth_dom + Vth_rec)/2 7V < VVBAT < 18V VEN = 5V 7V < VVBAT < 18V VEN = 5V 7V < VVBAT < 18V VHYS = Vth_rec - Vth_dom 7V < VVBAT < 18V THrec(max) = 0.744 x VVBAT THDom(max) = 0.581 x VVBAT tBit = 50 s D1 = tBus_rec(min)/(2 x tBit) Load1: 1 nF + 1 k Load2: 10 nF + 500 7V < VVBAT < 18V THrec(min) = 0.422 x VVBAT THDom(min) = 0.284 x VVBAT tBit = 50 s D2 = tBus_rec(max)/(2xtBit) Load1: 1 nF + 1 k Load2: 10 nF + 500
8
IBUS
100
A
A
8
VBUS_CNT VBUSdom VBUSrec VBUShys
0.475 x VVBAT
0.5 x VVBAT
0.525 x VVBAT 0.4 x VVBAT
V
A
4.15 Receiver dominant state 4.16 Receiver recessive state 4.17 Receiver input hysteresis
8 8 8
V V
A A A
0.6 x VVBAT 0.175 x VVBAT
V
4.18 Duty cycle 1
8
D1
0.396
A
4.19 Duty cycle 2
8
D2
0.581
A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
20
ATA6823
4856I-AUTO-02/10
ATA6823
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. Parameters Test Conditions 7V < VVBAT < 18V THrec(max) = 0.778 x VVBAT THDom(max) = 0.616 x VVBAT tBit = 96 s D3 = tBus_rec(min)/(2 x tBit) Load1: 1 nF + 1 k Load2: 10 nF + 500 7V < VVBAT < 18V THrec(min) = 0.389 x VVBAT THDom(min) = 0.251 x VVBAT tBit = 96 s D4 = tBus_rec(max)/(2 x tBit) Load1: 1 nF + 1 k Load2: 10 nF + 500 7V < VVBAT < 18V trec_pd = max (trx_pdr, trx_pdf) 7V < VVBAT < 18V trx_sym = trx_pdr - trx_pdf Pin Symbol Min. Typ. Max. Unit Type*
4.20 Duty cycle 3
8
D3
0.417
A
4.21 Duty cycle 4
8
D4
0.590
A
4.22
Receiver propagation delay
13
trx_pd trx_sym TBUS -2
6
s
A
Symmetry of receiver 4.23 propagation delay rising edge minus falling edge 4.24 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7
13
+2
s
Dominant time for wake-up 7V < VVBAT < 18V via LIN-bus VLIN = 0V Control Inputs EN1, DIR, PWM, WD, TX Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Pull-up resistor Rise/fall time Debounce time EN1
(6)
8
30
90
150
s
A
12, 10, 11, 6, 9 12, 10, 11, 6, 9 12, 10, 11, 6, 9 EN1, DIR, PWM, WD TX 12, 10, 11, 6, 9 12, 10, 11, 6, 9 12
VIL VIH HYS RPD RPU trf tdb 2 x T100 0.7 x VVCC 0.3 25 25 0.5 50 50
0.3 x VVCC
V V
A A A A A D B
0.7 100 100 100 3 x T100
V k k ns s
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
21
4856I-AUTO-02/10
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Parameters Charge Pump Charge pump voltage Charge pump voltage Period charge pump oscillator CP load current in VG without CP load Load = 0A Load = 0A Load = 3 mA, CCP = 100 nF 21 21 21 24 24 21 21 VCP VCP T100 IVGCPz IVGCP VCPOK_UP VCPOK_DOWN TBD TBD 5.6 4.8 VVBAT + VVG - 1 9 11 0.6 4 TBD TBD VVBAT + VVG V V s mA mA V V A A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
CP load current in VG with Load = 3 mA, CP load CCP = 100 nF Charge pump OK threshold UP Charge pump OK threshold DOWN H-bridge Driver Low-side driver HIGH output voltage ON-resistance of sink stage of pins L1, L2 ON-resistance of source stage of pins L1, L2 Output peak current at pins VLx = 3V L1, L2, switched to LOW Output peak current at pins VLx = 3V L1, L2, switched to HIGH Pull-down resistance at pins L1, L2 ON-resistance of sink stage of pins H1, H2 ON-resistance of source stage of pins H1, H2 VSx = 0 VSx = VVBAT
26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 18, 20 18, 20
VLxH RDSON_LxL, x = 1, 2 RDSON_LxH, x = 1, 2 ILxL, x = 1, 2 ILxH, x = 1, 2 RPDLx x = 1, 2 RDSON_HxL, x = 1, 2 RDSON_HxH, x = 1, 2
VVG - 0.5V
VVG 20 20
V mA
A A A A A A A A
100 -100 30 140 20 20
mA k
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
22
ATA6823
4856I-AUTO-02/10
ATA6823
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. 7.9 Parameters Test Conditions Pin 18, 20 Symbol IHxL, x = 1, 2 IHxH, x = 1, 2 VHxL, VLxL x = 1, 2 VHxHstat1(7) RPDHx VVBAT + VVG - 1 30 Min. 100 Typ. Max. Unit mA Type* A = 13.5V V Output peak current at pins VBAT VSx = VVBAT Hx, switched to LOW VHx = VVBAT + 3V = 13.5V V Output peak current at pins VBAT VSx = VVBAT Hx, switched to HIGH VHx = VVBAT + 3V Static switch output low voltage at pins Hx and Lx VSx = 0V IHx = 1 mA ILx = 1 mA ILx = -10 A (PWM = static) VVBAT = VPBAT = 9V, I_VG = -20 mA
7.10
18, 20
-100
mA
A
7.11
18, 20, 26, 27
0.3
V
A
Static high-side switch 7.12 output high-voltage pins H1, H2 7.13 Sink resistance between Hx and Sx Dynamic Parameters
18, 20 17, 18, 19, 20
VVBAT + VVG 150
V
A
k
A
Propagation delay time, Figure 3-6 on page 13 7.15 low-side driver from high to VVBAT = 13.5V low Propagation delay time, 7.16 low-side driver from low to VVBAT = 13.5V high 7.17 Fall time low-side driver 7.18 Rise time low-side driver Propagation delay time, 7.19 high-side driver from high to low VVBAT = 13.5V CGx=5 nF VVBAT = 13.5V Figure 3-6 on page 13 VVBAT = 13.5V
26, 27
tLxHL
0.5
s
A
26, 27
tLxLH tLxf tLxr tHxHL
0.5 + tCC 0.5 0.5 0.5
s
A
26, 27 26, 27 18, 20
s s s
A A A
Propagation delay time, 7.20 high-side driver from low to VVBAT = 13.5V high 7.21 Fall time high-side driver 7.22 Rise time high-side driver 7.23 Cross conduction time 7.24 External resistor VVBAT = 13.5V, CGx = 5 nF VVBAT = 13.5V RCC = 10 k, CCC = 1 nF(8)
18, 20
tHxLH tHxf tHxr tCC RCC 3.75 5
0.5 + tCC 0.5 0.5 4.45
s
A
18, 20 18, 20 4 4
s s s k
A A A D
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
23
4856I-AUTO-02/10
8. Electrical Characteristics (Continued)
All parameters given are valid for VTHUV VVBAT VTHOV and for -40C ambient 125C unless stated otherwise. No. Parameters Test Conditions Pin 4 4
(9) (10)
Symbol CCC RONCC VSC tSC VVG VVGswitch
Min.
Typ.
Max. 5 200
Unit nF V s V V
Type* D A A A A A
7.25 External capacitor RON of tCC switching 7.26 transistor 7.28 Short circuit detection voltage VG regulator output voltage VG regulator output voltage switch mode Input EN2 Input low-voltage threshold Input high-voltage threshold Hysteresis Pull-down resistor Rise/fall time Debounce time Low level output current High level output current
(6) (6)
17, 19 17, 19 24 24
3.5 5 11 7
4 10
4.7 15 14 9
7.29 Short circuit detection time 7.30 7.31 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2
VVBAT = VPBAT = 18V, I_VG = -20 mA VVBAT = VPBAT = 9V, I_VG = -20 mA
32 32 32 32 32 32 15, 16
(6)
VIL VIH HYS RPD trf tdb IL IH
2.3 2.8 0.47 50 2 x T100 2 1 100
3.6 4.0
V V V
A A A A D B A A
200 100 3 x T100
k ns s mA mA
Diagnostic Outputs DG1, DG2, DG3 VDG = 0.4V(6) VDG = VCC - 0.4V 15, 16
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on TOSC; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc
24
ATA6823
4856I-AUTO-02/10
ATA6823
9. Application
9.1 General Remark
This chapter describes the principal application for which the ATA6823 was designed. Because Atmel(R) cannot be considered to understand fully all aspects of the system, application, and environment, no warranties of fitness for a particular purpose are given.
Table 9-1.
Component CVINT CVCC CCC RCC CVG CCP CVRES RRWD RLIN CLIN
Typical External Components
Function Blocking capacitor at VINT Blocking capacitor at VCC Cross conduction time definition capacitor Cross conduction time definition resistor Blocking capacitor at VG Charge pump capacitor Reservoir capacitor Watchdog time definition resistor Pull-up resistor for LIN bus (master only) Filter capacitor for LIN bus Value 220 nF, 10V, X7R 2.2 F, 10V, X7R Typical 330 pF, 100V, COG Typical 10 k Typical 470 nF, 25V, X7R Typical 220 nF, 25V, X7R Typical 470 nF, 25V, X7R Typical 51 k Typical 1 k Typical 220 pF, 100V 50% Tolerance 50% 50%
10. Errata
10.1 Faulty Pulse at DG1
A faulty pulse of approximately 100 ns appears at pin 16 (DG1), signalizing short circuit condition, under following circumstances: General condition: PWM = HIGH and detected undervoltage of VBAT (signalized at pin 15 = DG2) or detected overvoltage of VBAT (signalized at pin 15 = DG2) or detected undervoltage of the charge pump (signalized at pin 15 = DG2) or overtemperature shutdown.
10.2
Problem Fix/Workaround
Set the software to ignore the faulty pulse.
25
4856I-AUTO-02/10
11. Ordering Information
Extended Type Number ATA6823-PHQW Package QFN32 Remarks Pb-free
12. Package Information
Package: QFN 32 - 7 x 7 Exposed pad 4.7 x 4.7 Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 32 1 24 25 32 1
technical drawings according to DIN specifications +0
7 4.7
8 0.3 0.6
17 16 0.65 nom. 4.55 9
8
Drawing-No.: 6.543-5097.01-4 Issue: 1; 24.02.03
26
ATA6823
4856I-AUTO-02/10
ATA6823
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4856I-AUTO-01/10 History * Section 8 "Electrical Characteristics" number 7.31 on page 24 changed * LIN 2.0 to LIN 2.1 in whole document changed * Section 6 "Operating Range" on page 16 changed * LIN Transceiver part in Section 8 "Electrical Characteristics" on pages 19 to 21 changed * * * * * * * * * * * * 4856F-AUTO-01/08 4856E-AUTO-07/07 Section 3 "General Statement and Conventions" on page 4 deleted Section 4 "Application" from page 5 to page 24 removed Figure 3-1 "Wake-up by pin LIN" on page 7 changed Section 4 "Absolute Maximum Ratings" on page 15 changed Section 5 "Thermal Resistance" on page 15 changed Section 6 "Operating Range" on page 16 changed Section 7 "Noise and Surge Immunity, ESD and Latch-up" on page 16 added Section 8 "Electrical Characteristics" on pages 17 to 23 changed Section 10 "Schaffner and Electromagentic Compatibility" on pages 24 to 26 deleted Table 9-1 "Typical External Components" on page 24 changed Section 10 "Errata" on page 24 added Section 11 "ESD and Latch-up Requirements" on page 26 deleted
4856H-AUTO-07/09
4856G-AUTO-01/09
* Section 5.4 "5V/3.3V VCC Regulator" on pages 8 to 9 changed * Section 10 "Electrical Characteristics" number 3.3 on page 18 changed * Section 12 "Ordering Information" on page 27 changed * Put datasheet in a new template
27
4856I-AUTO-02/10
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
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Product Contact
Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts
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4856I-AUTO-02/10

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